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1 features ? all functions and channel selections are controlled by serial bus rf part ? all oscillators and pll integrated ? if converter ? fm demodulator ? rssi low frequency part ? asymmetrical input of microphone amplifier ? asymmetrical output of earpiece amplifier ? compander ? power supply management ? serial bus application ? ct0 standard ? narrowband voice and data transmitting/receiving systems description the programmable single-chip multichannel cordless phone ic includes all necessary low frequency parts such as microphone- and earphone amplifier, compander, power- supply management as well as all rf parts such as if converter, fm demodulator, rssi, oscillators and pll. several gains and mutes in transmit and receive direction are controlled by the serial bus. the compander can be bypassed. single-chip cordless telephone ic u3600bm preliminary rev. 4516c?ct0?08/02
2 u3600bm 4516c?ct0?08/02 figure 1. block diagram mixer1 vco3 :2 sin cos f lo mixert +45 -45 crystal mixer2 if rssi :n :k phase f lo f ref3 f lo vco2 loop :d2 :m12 :d1 :2 vco1 :d3 f ref1 :2 :10 :m serial bus bias bat low detector -+ d a muxda 1.5v - + expander demo- ear - + mic vrmic compressor limiter spl 1.5v datrx :m12 mix1in2 mix1in1 mix1o oscgnd xck vaf mix2 o mix2gnd mix2in ifin1 ifin2 etc exin reco1 reco2 rxo dain mic mico coin ctc cout limin txo opin opout daco d c vss vdd modin lfgnd mlf vrf vbias agnd rfovb rfo rfognd pclo lo1 lo2 gndlo oscillator comparator (3) (2) (1) filter phase comparator phase comparator f ref2 - + 1 1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 3 4 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 f mod dulator amp amp amp (1): pll1: modulator pll (2): pll2: mixer pll (3): pll3: local oscillator (lo) pll
3 u3600bm 4516c?ct0?08/02 pin configuration figure 2. pinning sso44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 lo1 lo2 gndlo mix1in1 mix1o oscgnd xck vaf mix2o mix2in ifin1 ifin2 etc exin reco1 reco2 rxo dain mic mico rfognd rfo rfovb agnd vbias vrf lfgnd modin vss daco opout opin txo limin cout ctc coin c pclo mix1in2 mix2gnd d vdd mlf
4 u3600bm 4516c?ct0?08/02 pin description pin symbol function 1 pclo phase comparator local oscillator 2 rfognd rf transmit output ground 3 rfo rf transmit output 4 rfovb power supply input of rf transmit output buffer 5 agnd analog ground for rf part 6 vbias decoupling capacitor of current reference 7 vrf supply voltage for rf part 8 mlf modulator loop filter 9 lfgnd modulator loop filter ground 10 modin modulator input 11 vdd supply voltage output for peripherals and internal supply of digital part 12 vss ground for lf analog and digital 13 d data input of serial bus 14 c clock input of serial bus 15 daco d/a and data comparator output 16 opout operational amplifier output 17 opin operational amplifier input (inverting) 18 txo output of limiter amplifier 19 limin limiter input 20 cout compressor output 21 ctc compressor time constant control analog output 22 coin compressor input 23 mico microphone amplifier output 24 mic inverting input of microphone amplifier 25 dain data comparator input 26 rxo output of demodulator 27 reco2 symmetrical output of receive amplifier 28 reco1 29 exin expander input 30 etc expander time constant control analog output 31 ifin2 symmetrical input of if amplifier 32 ifin1 33 mix2in input of mixer2 34 mix2gnd if amplifier and mixer2 ground 35 mix2o mixer2 output 36 vaf supply voltage for af/if parts 37 xck crystal oscillator input 11.15 mhz 38 oscgnd oscillator ground 39 mix1o output of mixer1 40 mix1in1 symmetrical input of mixer1 41 mix1in2 42 gndlo ground of lo 43 lo2 tank elements for lo are connected to these pins 44 lo1
5 u3600bm 4516c?ct0?08/02 system description radio frequency ic for analog cordless telephone application in 26/50 mhz band (cto standard). the ic performs full duplex communication. the transmitting and receiving frequency are depending on whether the ic is used in the handset or in the base station. frequency converter comprise an fm transmitter with switchable output power and first receiver mixer in the same unit. a two-wire bus interface can be used for the frequency control as well as for switching the transmitter power amplifier and the receiver. fine frequency adjust of reference quartz oscillator is programmable. the receive part is designed for a double conversion architecture. the incoming radio frequency signal will be filtered and amplified before reaching the first mixer. at this stage the rf signal will be converted down to the first intermediate frequency (10.7 mhz) by using a crystal oscillator (lo1). the transmit part contains two pll controlled vcos. the frequency modulation is accomplished by super-posing the incoming audio signal on the pll control voltage. final frequency is a product of mixing vco1 with first local oscillator of receiver part (vco3). the fm modulated carrier is amplified by externals power amplifier before entering the output filter and the antenna connector. adjustments for vco1 and vco2 to be able to use a wide frequency range for the vcos (i.e., vco2 26.3 mhz to 49.9 mhz) the two internal vcos (vco1 and vco2, i.e., the vcos of the transmit part) have a rough adjust and a fine adjust to increase the frequency range given by the phase comparator. the rough adjusts for these vcos are correlated with the country setting. for every country there are two sets of vco rough adjust settings, one for the base and one for the handset. see tables at channels frequencies and dividers. to compensate the variation in production there is a fine adjust for each of the vcos. the fine adjusts of the internal vcos could be set manually (for test purposes) or set by the automatic mode. theoretically the sign of the changing (increase/ decrease when the voltage of the phase comparator is to high) is selectable, but we need value 1 () in all cases. setting vco1 (vco2) under normal conditions: eafa1 (eafa2) = 1, automatic fine adjust vco1(vco2) enabled safa1 (safa2) = 1, sign of auto fine adjustment of vco1 (vco2) = 1. adjustment for vco3 in order to increase the adjustment range of vco3 with fixed external tank elements and/or for ?band switching?, especially for us frequencies, vco3 has programmable capacitors inside. these capacitors can be added by serial bus (fa3 [4:0]) between lo1 and lo2. there are 31 steps available, every step adding a capacitor of 0.5pf. speed-up of the loop filter of pll1 (?modulator pll?) to have a fast locking time for the modulator loop there is a precharge and a speed-up mode for the external loop filter. during receive mode (vco3 enabled, vco1 disabled) the modulator loop filter is precharged to about half of the internally regulated 2.5 v charge-pump voltage. during the first 30 ms after enabling vco1 the modulator phase comparator is in speed- up mode. in this mode the current of the pase comparator which charges the loop filter is much larger than in normal mode. additionally to the automatically switched 30 ms speed-up mode, the speed-up can be activated for any time by setting the bit su1.
6 u3600bm 4516c?ct0?08/02 speed-up of the loop filter of pll3 (?1st. lo.?) similiar to pll1, there is also a possibility to increase the locking speed of pll3. this can be done by setting the bit su3. having done this, the charge pump at the output of the phase comparator has a bigger current capability and therefore charges the external capacitors faster. adjustment of the modulator gain to fulfil the different requirements of the different countries three conversion gains of the modulator are selectable by the bits gmod [1:0] (r6: d2, d3). country settings see tables at channel frequencies and dividers. ranges see electrical characteristics at rf transmitter. modulator pll the fractional divider has been chosen to increase the reference frequency of the modulator pll. p 1 : integer part of the fractional divider (m = 1) q 1 : fractional part of the fractional divider (m = 1) the frequency step 2.5 khz is a fraction of the reference frequency 557.5 khz. in fact, the fractional divider divides q 1 times by (p 1 + 1) and (223 - q 1 ) times by p 1 during 223 cycles. for each comparison cycle (f ref1 = 557.5 khz), the accumulator content is incremented by the q 1 value and the divider divides by the p 1 value. when the accumulator value reaches or exceeds 223, the divider divides by the value (p 1 + 1). then, the accumulator holds the excess value (accumulator value - 223). after 223 cycles, the correct division is executed. serial bus interface the circuit is remoted by an external microcontroller through the serial bus. the data is a 12-bit word: a0 - a3: address of the destination register (0 to 15) d7 - d0: contents of register the data line must be stable when the clock is high and data must be serially shifted. after 12 clock periods, the transfer to the destination register is (internally) generated by a low to high transition of the data line when the clock is high. 557.5 khz f mod / p 1 q 1 223 --------- - + = q 1 223 f mod 557.5 khz -------------------------- - p 1 ? = 223 557.5 khz 2.5 khz -------------------------- - = q 1 p 1 1 + 223 q 1 ? p 1 + 223 ---------------------------------------------------------------------------- - p 1 q 1 223 --------- - + =
7 u3600bm 4516c?ct0?08/02 figure 3. serial bus figure 4. serial bus transmission figure 5. serial bus structure micro- processor d clock c data word transmission transfer condition 2nd word 1st word data (d) clock (c) d0 d1 d2 a1 a2 a3 a0 data clock address decoder latches commands 4 8 128 0 15
8 u3600bm 4516c?ct0?08/02 figure 6. serial bus timing diagram content of internal registers the registers have the following structure r0: reference for d/a converter muxda: d/a multiplexing vbat / rssi da(0:6): reference voltage d/a r1: gain of earpeace amplifier and demodulator gea[0:4]: gain of earpeace amplifier; ?0? is lsb, ?4? is msb gdem: demodulator gain (1 = low gain) r2: switches and mutes for receive and data reception datrx: switch data comparator output to ?daco?-pin bexp: bypass expander eea: enable earpiece amplifier erxo: enable rxo output driver erx1: enable rx low frequency part 1 erxhf: enable mixer2 and if-amplifier mrx: mute rx low frequency path (expander) keeping circuit enabled erx2: enable rx low frequency part 2 (expander) r3: switches and mutes for transmit and power managemant pdvdd: enable pull-down transistor in power-down mode rbat: battery detection high/low range mtx: mute tx low frequency path (compressor) keeping circuit enabled etx: enable tx low frequency part a1 a2 a3 data (d) clock (c) d0 tsud thd tch tcl teon teh teoff d7 d6 d5 d4 d3 d2 d1 d0 muxda da6 da5 da4 da3 da2 da1 da0 gea4 gea3 gea2 gea1 gea0 gdem free free datrx bexp eea erxo erx1 erxhf mrx erx2 pdvdd rbat free free free free mtx etx
9 u3600bm 4516c?ct0?08/02 r4: free (not used, for future extensions ) r5: gain vco2 kv2[1:3]: gain of vco2 m12: double phase comparator frequency of pll2 r6: miscellaneus settings in synthesizer part etxo: enable hf-transmit output m1cp: changes 1 db compression point and current consumption of mixer1 (?0? ?> high, ?1? ?> low) frmt: output frequency range of mixert imixi: invert inputs of phase comparator in pll2 gmod[0:1]: modulation gain of vco1 su1: speed-up phase comparator for pll1 (tm): enable the internal test mode. it is mandatory that tm is kept to ?0?! (if not 0, the circuit will not work as expected or described here in this paper) r7: pll1 setting dr1i[0:1]: additional divider reference frequency pll1 ra1[0:1]: rough adjustment vco1 dv1i[0:3]: divider setting pll1 integer part; ?0? is lsb, ?3? is msb r8: divider pll1 fractional part dv1f[0:7]: divider setting pll1 fractional part; ?0? is lsb, ?7? is msb r9: divider pll3 lsbs r10: divider pll3 msbs and msb of vco3 fine adjustment fa34: fine adjustment vco3 (frequency reduction) msb dv1i[0:14]: divider setting pll3 integer part; ?0? is lsb, ?14? is msb free free free free free free free free free free kv23 kv22 kv21 m12 free free etxo m1cp frmt imixi gmod1 gmod0 su1 (tm) dr1i1 dr1i0 ra11 ra10 dv1i3 dv1i2 dv1i1 dv1i0 dv1f7 dv1f6 dv1f5 dv1f4 dv1f3 dv1f2 dv1f1 dv1f0 dv3i7 dv3i6 dv3i5 dv3i4 dv3i3 dv3i2 dv3i1 dv3i0 fa34 dv3i14 dv3i13 dv3i12 dv3i11 dv3i10 dv3i9 dv3i8
10 u3600bm 4516c?ct0?08/02 r11: setting pll2 and vco3 fa3[0:4]: fine adjustment of vco3 (frequency reduction); ?0? is lsb, ?4? is msb amix[1:2]: lengthening antibacklash signal pll2 ra2[1:0]: rough adjustment vco2 r12: divider for country setting, fine adjustment oscillator faos[0:2]: fine adjustment of crystal oscillator (frequency reduction); ?0? is lsb, ?2? is msb d3[0:1]: setting divider d3 d20: setting divider d2 d1[0:1]: setting divider d1 r13: vco1 enable and fine adjustment evco1: enable vco1 safa1: sign for automatic fine adjustment of vco1 eafa1: enable automatic fine adjustment of vco1 fa1(0:4): manual fine adjustment of vco1 (frequency reduction); ?0? is lsb, ?4? is msb r14: vco2 enable and fine adjustment evco2: enable vco2 and mixert safa2: sign for automatic fine adjustment of vco2 eafa2: enable automatic fine adjustment of vco2 fa2(0:4): manual fine adjustment of vco2 (frtequency reduction); ?0? is lsb, ?4? is msb r15: vco3 enable, speed-up and referencq frequency, crystal oscillator enable evco3: enable vco3 and mixer1 eosc: enable crystal oscillator (11.15 mhz) su3: speed-up phase comparator for pll3 e25k: selection phase comparator frequency for pll3: f ref3 = 25 khz e12k5: selection phase comparator frequency for pll3: f ref3 = 12.5 khz e10k: selection phase comparator frequency for pll3: f ref3 = 10 khz e6k25: selection phase comparator frequency for pll3: f ref3 = 6.25 khz e5k: selection phase comparator frequency for pll3: f ref3 = 5 khz e5k, e6k25, e10k, e15k5, e25k = 0: selection phase comparator frequency for pll3: f ref3 = 2.5 khz fa33 fa32 fa31 fa30 amix2 amix1 ra21 ra20 faos2 faos1 faos0 d31 d30 d20 d11 d10 evco1 safa1 eafa1 fa14 fa13 fa12 fa11 fa10 evco2 safa2 eafa2 fa24 fa23 fa22 fa21 fa20 evco3 eosc su3 e25k e12k5 e10k e6k25 e5k
11 u3600bm 4516c?ct0?08/02 absolute maximum ratings parameters symbol value unit supply voltage v batt , v dd 5.5 v junction temperature t j +125 c ambient temperature t amb ?25 to +75 c storage temperature t stg ?50 to +125 c power dissipation t amb = 60c p tot 0.9 w thermal resistance parameters symbol value unit junction ambient sso44 r thja 70 k/w electrical characteristics t amb = +25 c, vrf = vaf = rfovb = 3.6 v, all bits set to ?0?, unless otherwise specified. test circuit, see figure 7. crystal specifications, see table ?crystal specifications?. parameters test conditions symbol min. typ. max. unit power supply operating voltage range 3.1 3.6 5.2 v current consumption operating current in inactive mode (low voltage) vrf = vaf = rfovb = 2.9 v vdd = 0 v 30 65 85 a operating current in standby mode vrf = vaf = rfovb = 3.6 v 30 100 350 a operating current in rx mode ?waiting for rssi? erxhf = evco3 = eosc = 1 7.5 10.4 ma operating current in rx mode ?receiving data? erxhf = evco3 = eosc = erx1 = erxo = 1 8.5 11.5 ma operating current in conversation mode: all blocks enabled erxhf = evco3 = eosc = erx1 = erxo = erx2 = eea = evco2 = etxo = 1 no load at rfo pin 3 20 29 ma charge pump of ll1 charge pump output voltage output high 2.38 2.5 2.63 v precharge voltage at the loop filter sb127 = 1, sb119 = 0 1.15 1.4 1.65 v charge pump output current in speed-up mode vmlf = 1.25 v, output low 190 400 a vmlf = 1.25 v, output high -400 -190 a charge pump output current vmlf = 1.25 v, output low 4.3 6.2 8 a vmlf = 1.25 v, output high -8 -6.2 -4.3 a charge pump leakage current vmlf = 1.25 v, output tristate -150 +150 na charge pump of pll3 charge pump output voltage output high 2.38 2.5 2.63 v charge pump output current in speed-up mode vpclo = 1.25 v, output low 220 420 a vpclo = 1.25 v, output high -420 -220 a
12 u3600bm 4516c?ct0?08/02 charge pump output current vpclo = 1.25 v, output low 80 160 a vpclo = 1.25 v, output high -160 -80 a charge pump leakage current vpclo = 1.25 v, output tristate -50 +50 na receiver input mixer (mixer1) evco3 = eosc = 1 input frequency range 20 50 mhz output frequency 10.7 mhz input resistance mix1in1 / mix1in2 to gnd 3.0 k input capacitance mix1in1 / mix1in2 to gnd 3.5 pf output impedance mix1o 210 330 390 voltage gain mix1in1/2 -> mix1o ?loaded? (330 with serial capacitance) ?unloaded? 11.5 17.5 db db input noise voltage 9nv hz ?1/2 input 1-db compression point ?loaded? (330 with serial capacitance) m1cp=0 m1cp=1 ?unloaded? m1cp=1 140 40 100 mv mv mv third order input intercept point ?loaded? (330 with seial capacitance) m1cp=0 430 mv if mixer (mixer2) eosc = erxhf = 1; input frequency: 10.7 mhz input resistance mix2in to gnd 2.0 3.0 4.0 k input capacitance mix2in to gnd 2.5 3 3.5 pf output impedance mix2o 1200 1500 1800 voltage gain mix2in -> mix2o ?loaded? (1500 with serial capacitance) 13 15 17 db input 1-db compression point ?loaded? (1500 with serial capacitance) 32 mv third order input intercept point ?loaded? (1500 with serial capcitance) 80 mv if amplifier and demodulator erxhf=1, erx1=1, erxo=1; input signal: 450 khz, 500 v, fm-modulation frequency = 1 khz recovered audio at rxo, demodulator gain gdem=0 gdem=1 180 90 mv/khz mv/khz am rejection ratio 30% am, 2.5 khz fm 35 db expander erx2 = 1; 470 nf from etc to gnd (vss) gain reference level = g.r.l. (gain = 0 db) 70 80 90 mvrms gain versus input signal level (?gain tracking?) vexin = 10 db less than g.r.l. vexin = 20 db less than g.r.l. vexin = 30 db less than g.r.l. ?11 ?21 ?35 ?10 ?20 ?30 ?9 ?19 ?25 db db db attack time vexin = step 25 mv ?> 50 mv measure time after step, when output voltage has 0.75 times of final value 16 ms electrical characteristics (continued) t amb = +25 c, vrf = vaf = rfovb = 3.6 v, all bits set to ?0?, unless otherwise specified. test circuit, see figure 7. crystal specifications, see table ?crystal specifications?. parameters test conditions symbol min. typ. max. unit
13 u3600bm 4516c?ct0?08/02 release time vexin = step 50 mv ?> 25 mv measure time after step, when output voltage has 1.5 times of final value 16 ms input resistance 9.5 15 k earpiece amplifier eea = 1, erx2 = 1, bexp = 1; apply input voltage to exin; measure differentially at reco1/2 minimum gain gea[4:0]=0 0 1 2 db medium gain gea[4:0]=16 16 17 18 db maximum gain gea[4:0]=31 31 32 33 db gain adjust step 0.8 1 1.2 db output voltage swing maximum gain; 1 k load; increase input voltage until distortion 5% 4.8 5 vpp input resistance 7.3 12.5 k if amplifier: rssi input frequency erxhf=1 450 khz input resistance 1.6 2.0 2.5 k rssi sensitivity vif = 0 v starting from 0 increase rssi-level until mean of sampled signal at daco is 0.5. rssi-level = ion0 vif = 25.4 v, f = 450 khz increase rssi level again until mean of sampled signal at daco is 0.5. rssi-level = ion1 rssi-sensitivity = ion1-ion0 1 rssi input voltage dynamic range 65 db rssi level number of programmable steps (see folowing table ?rssi level programming (typical values) 127 db rssi level step size in the logarithmic region 0.35 0.46 0.6 db electrical characteristics (continued) t amb = +25 c, vrf = vaf = rfovb = 3.6 v, all bits set to ?0?, unless otherwise specified. test circuit, see figure 7. crystal specifications, see table ?crystal specifications?. parameters test conditions symbol min. typ. max. unit rssi level programming (typical values) input voltage vif ( v) rssi level (decimal) 05 25.4 8 42.4 14 424 54 4240 97 42400 111
14 u3600bm 4516c?ct0?08/02 electrical characteristics (continued) t amb = +25 c, vrf = vaf = rfovb = 3.6 v, all bits set to ?0?, unless otherwise specified. test circuit, see figure 7. parameters test conditions symbol min. typ. max. unit data comparator erx1 = datrx = 1 hysteresis 50 mv threshold voltage 1.5 v input impedance dain 100 k output high voltage daco, without load (cmos-output ?> full swing) 3.5 v output low voltage daco, without load (cmos-output ?> full swing) 0.1 v output impedance daco 6 k battery switch ?off? threshold decrease vbat until internal switch between vbat and vdd becomes high ohmic (?off?) 2.85 2.95 3.1 v ?on? threshold increase vbat until internal switch between vbat and vdd becomes low ohmic (?on?) 3.1 3.2 3.35 v hysteresis difference between on and off threshold 250 mv ?off?-leakage current 10 a switch ?on?-resistance 50 battery management muxda = 1 maximum bat low da[6:0] = 127, rbat = 1 3.7 3.95 4.1 v minimum bat low over switch da[6:0] = 27, rbat = 1 3.05 3.2 3.35 v maximum bat high da[6:0] = 127, rbat = 0 4.75 5.05 5.25 v minimum bat high da[6:0] = 0, rbat = 0 3.83 4.1 4.27 v adjust step 3.5 7.5 11.5 mv maximum - minimum 852.5 952.5 1052.5 mv microphone amplifier etx=1 open loop gain 80 db gain bandwidth product 3mhz input noise voltage, bw = 300 hz to 3.4 khz, psophometrically weighted 0.8 2 vrmsp compressor etx = 1; 470 nf from ctc to gnd (vss) gain reference level = g.r.l. (gain = 0 db) 298 316 340 mvrms gain versus input signal level (?gain tracking?) vcoin = 20 db less than g.r.l. vcoin = 40 db less than g.r.l. vcoin = 50 db less than g.r.l. vcoin = 60 db less than g.r.l 9 19 22 10 20 25 30 11 21 28 db attack time vcoin = step 31.6 mv ?> 126 mv, (-30 dbv ?> ?18 dbv) measure time after step, when output voltage has 1.5 times of final value 3.5 ms
15 u3600bm 4516c?ct0?08/02 release time vcoin = step 126 mv ?> 31.6 mv (-18 dbv ?> -30 dbv) measure time after step, when output voltage has 0.75 times of final value 14.4 ms input resistance 14 19.5 26 k splatter amplifier etx = 1 open loop gain 90 db gain bandwidth product 150 khz maximum output voltage swing 2.4 vpp limiter amplifier etx = 1, tj = 25c gain for signals below limitation limin ?> txo, 20 mv rms applied to limin (ac coupled) 26 db distortion for signals below limitation limin ?> txo, 20 mv rms applied to limin (ac coupled) 2% maximum output voltage swing (above limitation, clipping) 1.8 2.1 2.35 v pp input resistance at limin 15 20 25 k remark: the gain and maximum output voltage swing of the limiter amplifier changes with temperature to compensate the temperature dependancy of modin (?tx conversion gain? of rf transmit part), fundamentally determined by the structure of the circuitry. rf transmitter etxo = evco1 = evco2 = evco3 = eosc = 1; t j = 25c modin input impedance 70 100 130 k rfo output impedance load = 200 ? 230 300 390 rfo output voltage level etxo = 0; no load 0.3 v highest operating frequency usa base channel 9 (us1b9) 49.99 00 mhz tx conversion gain modin - rfo for the complete programming see ?channel frequencies, dividers and country settings? on page 19? usa1: gmod[1:0] = 00; fmod = ~7.6 mhz usa2: gmod[1:0] = 01; fmod = ~5.7 mhz france: gmod[1:0] = 01; fmod = 4.3 mhz gmod[1:0] = 00; fmod = 4.3 mhz spain/netherlands: gmod[1:0] = 10; fmod = 1.8 mhz 5.2 5.2 3.8 2.7 7.9 khz/v khz/v khz/v khz/v khz/v demodulated distortion thd modin - rfo modulation frequency: 1 khz us: f = 4.0 khz france: f = 2.5 khz 1.5 5 % electrical characteristics (continued) t amb = +25 c, vrf = vaf = rfovb = 3.6 v, all bits set to ?0?, unless otherwise specified. test circuit, see figure 7. parameters test conditions symbol min. typ. max. unit
16 u3600bm 4516c?ct0?08/02 . remark: the tx conversion gain of the rf transmitter is somehow dependent on temperature. this is determined by the fundamental princip le of this circuitry. means have been taken inside the limiter amplifier, being in the signal path before modin, which are able to completely compensate this temperature behavior. logical part inputs: c, d low voltage input high voltage input input leakage current (0 < vi < vdd) vil vih ii 0.8 v dd ?1 0.2 v dd +5 a input leakage current pin xck (0 < vi < vdd) ?5 +5 a serial bus (figure 8) data set-up time data hold time clock low time clock high time hold time before transfer condition data low pulse on transfer condition data high pulse on transfer condition tsud thd tcl tch teon teh teoff 0.1 0 2 2 0.1 0.2 0.2 s s s s s s s electrical characteristics (continued) t amb = +25 c, vrf = vaf = rfovb = 3.6 v, all bits set to ?0?, unless otherwise specified. test circuit, see figure 7. parameters test conditions symbol min. typ. max. unit fine adjustment of the oscillator frequency to set the frequency of the oscillator exact to 11.15 mhz, the frequency is adjustable in 8 steps, by adding 3 different internal capacities the frequency could be reduced. parameters test conditions / pins min. typ. max. unit oscillator frequency without reduction faos (0:2) = 0 11.15 + mhz changing of oscillator frequency with fosc reduction faos2 faos1 faos0 0 0 1 0 1 0 1 0 0 1 0 1 140 280 560 700 hz
17 u3600bm 4516c?ct0?08/02 figure 7. test circuit vaf c i n u 3 6 0 0 b m xck vdd vbias vrf vaf txo rxo rfovb rfognd rfo reco2 reco1 pclo oscgnd opout opin modin mlf mix2o mix2in mix2gnd mix1o mix1in2 mix1in1 mico mic lo2 lo1 limin lfgnd ifin2 ifin1 gndlo ein etc dain daco data ctc cout cin clock agnd vss 1 2 2 2 3 4 4 v d d 470n c o u t modin 4 7 0 n r f o v b 4 7 0 n daco 4 . 7 n 4 7 0 n reco1 reco2 rxo dain 2 2 0 n 220n m i c i n m i c o 2 2 u f ifin2 10n 470n 10n mix2o 1 0 n mix1o mix2in 10n 1 0 n 0 1 mix1in1 10n 1 1 . 1 5 m 1 2 tx-/modulator- loop filter r f o i n t e r f a c e m p u s e r i a l bzt55c51 mix1in2 10n 5p 1 0 n 6 8 n 1u 100n 10n ifin1 470n 4 7 n s p l a i n l i m i n c o u t o p o u t 4 7 n 4 4 k 8 5 850 1 0 0 0 1500 330 5.6k 56k 24k 1 0 k 1 0 k data clock ein vrf t h i s s c h e m a t i c s i s o n l y a b a s i c ( s i m p l i f i e d ) r e p r e s e n t a t i o n o f t h e c u r r e n t p r o d u c t i o n t e s t c i r c u i t n o t e :
18 u3600bm 4516c?ct0?08/02 figure 8. application circuit m i x e r 1 v c o 3 : 2 s i n c o s f l o m i x e r t + 4 5 - 4 5 c r y s t a l m i x e r 2 i f - a m p r s s i : n : k p h a s e f l o f r e f 3 f l o v c o 2 l o o p : d 2 : m 1 2 : d 1 : 2 v c o 1 : d 3 : ( p m + ) q m 2 2 3 f r e f 1 : 2 : 1 0 : m s e r i a l b u s b i a s b a t l o w d e t e c t o r - + d a m u x d a 1 . 5 v - + e x p a n d e r d e m o d u l a t o r e a r a m p - + m i c v r m i c c o m p r e s s o r l i m i t e r s p l a m p 1 . 5 v d a t r x : m 1 2 o s c i l l a t o r c o m p a r a t o r ( 3 ) ( 2 ) ( 1 ) f i l t e r p h a s e c o m p a r a t o r p h a s e c o m p a r a t o r f r e f 2 - + 4 7 p 4 7 p r x r x g n d 1 1 . 1 5 m h z 3 9 0 1 0 0 n s f e 1 0 . 7 m s 2 c f w 4 5 0 e 5 . 6 k 4 7 0 n 2 2 0 n 1 k 7 . 5 k 2 0 k 8 . 2 k 2 2 n 0 . 7 5 n 1 0 0 n 1 5 n 2 2 n 2 . 2 k 2 2 k 4 7 0 n 2 2 0 n e l e c t r e t m i c r o - 4 7 0 n 4 . 7 k 2 . 2 n 1 2 k 5 6 n 1 0 0 k 1 5 n t x d a t a 1 0 k 1 5 k 1 n 1 2 n 1 2 k c d v d d d a c o 1 0 k 4 . 7 n 5 . 6 k 1 0 0 n 1 u + v b 1 0 2 . 2 k 1 n 2 0 3 3 0 1 0 0 n 1 u h 5 . 6 p 6 8 n 1 0 n 2 4 k 5 6 k h a n d : 1 0 0 n h b a s e : 2 3 0 n h 2 x b z t 5 5 c 5 1 duplex filter antenna t x g n d t x + v b 1 0 0 n 1 0 0 n 1 0 0 n 1 1 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 2 3 4 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 + v b 1 0 0 n f m o d ( 1 ) : p l l 1 : m o d u l a t o r p l l ( 2 ) : p l l 2 : m i x e r p l l ( 3 ) : p l l 3 : l o c a l o s c i l l a t o r ( l o ) p l l c p h o n e
19 u3600bm 4516c?ct0?08/02 channel frequencies, dividers and country settings to meet all requirements of various countries ? france (f), spain (e), netherlands (nl), usa, portugal (p), taiwan, new zealand and korea ? and modes ? base (b), handset (h) ? several bits have to be set which do not change for the different channels. these settings are called country settings. ? the country-setting bits contain: ? rough adjustments for 2 vcos ? setting three integer divider in the mixer pll and modulator pll ? conversion gain adjustment of mixer pll ? modulator gain ? setting of the pulling direction of pll2 (value dependent, if tx frequency is higher or lower than lo frequency) ? demodulator gain note: setting the fractional dividers: for n, q m , send the binary equivalent of the numbers given below. for p m (integer part of modulator pll), send the d2 complement (16 ? p m ) i.e., fb1 (p m = 7, q m = 159 => integer: send 16 ?p m = 9, fractional: send 159) name register function notes number of positions ra1[1:0] rough adjust vco1 00: is the highest frequency 3 ra2[1:0] rough adjust vco2 00: is the highest frequency 4 d1[1:0] integer divider d1 division by 2, 4, 6, 8 4 d20 integer divider d2 division by 6, 8 2 m12 integer divider m12 doubles reference frequency of pll2 when set to ?1? 2 d3[1:0] integer divider d3 division by 1, 2, 4 3 kv[3:1] conversion gain vco2 6 gmod[1:0] modulator gain 00: gain minimal 3 imixi reverse inputs of pc of pll 0: if fvco2 lower than fvco3 2 dr1[1:0] additional divider m for reference frequency f ref1 ?0? means no reduction, >0 only necessary in e, nl, portugal 4 frmt frequency range mixer t 0: output frequency < 5 mhz 2 gdem demodulator gain 0: high gain 1: low gain 2
20 u3600bm 4516c?ct0?08/02 tables for programming of the dividers (refer to block diagram) divider m for reference frequency of pll1: there are several countries like spain, the netherlands and portugal with relatively low modulator frequencies fmod. in case of modulation there will be a big maximum time shift between pulses coming from fractional divider and pulses coming from reference frequency divider. as a consequence the phase comparator enters an undesired opera- tion mode. to avoid entering this operation mode the reference frequency f ref1 has to be reduced by a factor m. simultaneously, keeping f mod constant, the factors of fractional dividers have to be changed as well. the connection between the additional reference frequency divider m and the factors p m and q m of fractional divider is given below. the subscript m denotes which value of m refers to the factors p m and q m of fractional divider. the formulas take into account that the numerator of the fraction q m /223 must not exceed 223. p m = p 1 m + integer (q m/223) q m = q 1 m - 223 integer (q 1 m/223) divider d1 for pll2: d11 (bit) d10 (bit) decimally d1 (block diagram),if m12 = 0 d1 (block diagram),if m12 = 1 000 2 1 011 8 4 102 6 3 113 4 2 divider d2 between pll1 and pll2: d20 (bit) decimally d2 (block diagram),if m12 = 0 d2 (block diagram),if m12 = 1 006 3 018 4 divider d3 for pll1: d31 (bit) d30 (bit) decimally d3 (block diagram) 000 1 011 2 102 6 113 4
21 u3600bm 4516c?ct0?08/02 france modulation loop frequency and divider f mod = 4.3 mhz, p m = 7, q m = 159, m = 1 france base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 00 11 11 1 01 100 01 (1) 00000 value max min d1 = 4 d2 = 8 d3 = 2 supra m = 1 low high gain note: 1. alternatively, gmod[1:0] could be set to ?00?. this reduces the tx conversion gain (modin ?> rfo) from about 3.8 khz/v to about 2.7 khz/v, a value, which should be still sufficient for a maximum f of 2.5 khz that is useful in the french case. channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 26.3125 41.3125 30.6125 4898 2 26.3250 41.3250 30.6250 4900 3 26.3375 41.3375 30.6375 4902 4 26.3500 41.3500 30.6500 4904 5 26.3625 41.3625 30.6625 4906 6 26.3750 41.3750 30.6750 4908 7 26.3875 41.3875 30.6875 4910 8 26.400 41.4000 30.7000 4912 9 26.4125 41.4125 30.7125 4914 10 26.4250 41.4250 30.7250 4916 11 26.4375 41.4375 30.7375 4918 12 26.4500 41.4500 30.7500 4920 13 26.4625 41.4625 30.7625 4922 14 26.4750 41.4750 30.7750 4924 15 26.4875 41.4875 30.7875 4926
22 u3600bm 4516c?ct0?08/02 france modulation loop frequency and divider f mod = 4.3 mhz, p m = 7, q m = 159, m = 1 france hand country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 00 01 11 1 01 101 01 (1) 10000 value max d1 = 4 d2 = 8 d3 = 2 infra m = 1 low high gain note: 1. alternatively, gmod[1:0] could be set to ?00?. this reduces the tx conversion gain (modin ?> rfo) from about 3.8 khz/v to about 2.7 khz/v, a value, which should be still sufficient for a maximum f of 2.5 khz that is useful in the french case. channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 41.3125 26.3125 37.0125 5922 2 41.3250 26.3250 37.0250 5924 3 41.3375 26.3375 37.0375 5926 4 41.3500 26.3500 37.0500 5928 5 41.3625 26.3625 37.0625 5930 6 41.3750 26.3750 37.0750 5932 7 41.3875 26.3875 37.0875 5934 8 41.4000 26.4000 37.1000 5936 9 41.4125 26.4125 37.1125 5938 10 41.4250 26.4250 37.1250 5940 11 41.4375 26.4375 37.1375 5942 12 41.4500 26.4500 37.1500 5944 13 41.4625 26.4625 37.1625 5946 14 41.4750 26.4750 37.1750 5948 15 41.4875 26.4875 37.1875 5950
23 u3600bm 4516c?ct0?08/02 spain modulation loop frequency and divider f ref1 = 557.5 khz/4, f mod = 1.8 mhz/4,p m = 12,q m = 204, m = 4 spain base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 10 00 1 11 001 10 1 11 1 1 value d1 = 2d2 = 8d3 = 4 infra m = 4 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 31.025 39.925 29.225 4676 2 31.050 39.950 29.250 4680 3 31.075 39.975 29.275 4684 4 31.100 40.000 29.300 4688 5 31.125 40.025 29.325 4692 6 31.150 40.050 29.350 4696 7 31.175 40.075 29.375 4700 8 31.200 40.100 29.400 4704 9 31.250 40.150 29.450 4712 10 31.275 40.175 29.475 4716 11 31.300 40.200 29.500 4720 12 31.325 40.225 29.525 4724
24 u3600bm 4516c?ct0?08/02 spain modulation loop frequency and divider f ref1 = 557.5 khz/4, f mod = 1.8 mhz/4,p m = 12,q m = 204, m = 4 spain hand country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 01 00 1 11 100 10 0 11 1 1 value high d1 = 2 d2 = 8 d3 = 4 high supra m = 4 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 39.925 31.025 41.725 6676 2 39.950 31.050 41.750 6680 3 39.975 31.075 41.775 6684 4 40.000 31.100 41.800 6688 5 40.025 31.125 41.825 6692 6 40.050 31.150 41.850 6696 7 40.075 31.175 41.875 6700 8 40.100 31.200 41.900 6704 9 40.150 31.250 41.950 6712 10 40.175 31.275 41.975 6716 11 40.200 31.300 42.000 6720 12 40.225 31.325 42.025 6724
25 u3600bm 4516c?ct0?08/02 netherlands modulation loop frequency and divider f ref1 = 557.5 khz/4, f mod = 1.8 mhz/4,p m = 12,q m = 204, m = 4 netherlands base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 10 00 1 11 001 10 1 11 1 1 value low d1 = 2 d2 = 8 d3 = 4 high infra m = 4 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 31.0375 39.9375 29.2375 4678 2 31.0625 39.9625 29.2625 4682 3 31.0875 39.9875 29.2875 4686 4 31.1125 40.0125 29.3125 4690 5 31.1375 40.0375 29.3375 4694 6 31.1625 40.0625 29.3625 4698 7 31.1875 40.0875 29.3875 4702 8 31.2125 40.1125 29.4125 4706 9 31.2375 40.1375 29.4375 4710 10 31.2625 40.1625 29.4625 4714 11 31.2875 40.1875 29.4875 4718 12 31.3125 40.2125 29.5125 4722
26 u3600bm 4516c?ct0?08/02 netherlands modulation loop frequency and divider f ref1 = 557.5 khz/4, f mod = 1.8 mhz/4,p m = 12,q m = 204, m = 4 netherlands hand country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 01 00 1 11 001 10 0 11 1 1 value high d1 = 2 d2 = 8 d3 = 4 high supra m = 4 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 39.9375 31.0375 41.7375 6678 2 39.9625 31.0625 41.7625 6682 3 39.9875 31.0875 41.7875 6686 4 40.0125 31.1125 41.8125 6690 5 40.0375 31.1375 41.8375 6694 6 40.0625 31.1625 41.8625 6698 7 40.0875 31.1875 41.8875 6702 8 40.1125 31.2125 41.9125 6706 9 40.1375 31.2375 41.9375 6710 10 40.1625 31.2625 41.9625 6714 11 40.1875 31.2875 41.9875 6718 12 40.2125 31.3125 42.0125 6722
27 u3600bm 4516c?ct0?08/02 u.k. modulation loop frequency and divider f ref1 = 557.5 khz/4, f mod = 1.8 mhz/4,p m = 12,q m = 204, m = 4 u.k. modulation loop frequency and divider f ref1 = 557.5 khz/4, f mod = 1.8 mhz/4,p m = 12,q m = 204, m = 4 u.k. base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 10 00 1 11 001 10 1 11 1 1 value low d1 = 2 d2 = 8 d3 = 4 high infra m = 4 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 31.0375 39.9375 29.2375 4678 2 31.0625 39.9625 29.2625 4682 3 31.0875 39.9875 29.2875 4686 4 31.1125 40.0125 29.3125 4690 u.k. handset country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 01 00 1 11 001 10 0 11 1 1 value high d1 = 2 d2 = 8 d3 = 4 high supra m = 4 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 39.9375 31.0375 41.7375 6678 2 39.9625 31.0625 41.7625 6682 3 39.9875 31.0875 41.7875 6686 4 40.0125 31.1125 41.8125 6690
28 u3600bm 4516c?ct0?08/02 usa base country setting channels (channel 1 ? 10, usa1): name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 00 01 1 00 100 00 1 00 1 1 value max d1 = 8 d2 = 8 d3 = 1 low infra m = 1 high low gain country setting new channels (channel 11 ? 25, usa2): name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 01 01 10 0 00 110 01 1 00 0 1 value high d1 = 6 d2 = & d3 = 1 infra m = 1 low low gain channel frequencies and 1st lo divider, f ref3 = 5 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 46.610 49.670 38.970 7794 2 46.630 49.845 39.145 7829 3 46.670 49.860 39.160 7832 4 46.710 49.770 39.070 7814 5 46.730 49.875 39.175 7835 6 46.770 49.830 39.130 7826 7 46.830 49.890 39.190 7838 8 46.870 49.930 39.230 7846 9 46.930 49.990 39.290 7858 10 46.970 49.970 39.270 7854 new channel channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 11 43.720 48.760 38.06 7612 12 43.740 48.840 38.14 7628 13 43.820 48.860 38.16 7632 14 43.840 48.920 38.22 7644 15 43.920 49.020 38.32 7664 16 43.960 49.080 38.38 7676 17 44.120 49.100 38.40 7680 18 44.160 49.160 38.46 7692 19 44.180 49.200 38.50 7700 20 44.200 49.240 38.54 7708 21 44.320 49.280 38.58 7716 22 44.360 49.360 38.66 7732 23 44.400 49.400 38.70 7740 24 44.460 49.460 38.76 7752 25 44.480 49.500 38.80 7760
29 u3600bm 4516c?ct0?08/02 usa hand country setting channels (channel 1 ? 10, usa1): name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 00 01 1 00 100 00 0 00 1 1 value max d1 = 8 d2 = 8 d3 = 1 supra m = 1 high low gain country setting new channels (channel 11 ? 25, usa2): name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 01 00 10 0 00 110 01 0 00 0 1 value high d1 = 6 d2 = & d3 = 1 supra m = 1 low low gain channel frequencies and 1st lo divider, f ref3 = 5 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 49.670 46.610 57.31 11462 2 49.845 46.630 57.33 11466 3 49.860 46.670 57.37 11474 4 49.770 46.710 57.41 11482 5 49.875 46.730 57.43 11486 6 49.830 46.770 57.47 11494 7 49.890 46.830 57.53 11506 8 49.930 46.870 57.57 11514 9 49.990 46.930 57.63 11526 10 49.970 46.970 57.67 11534 new channel channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 11 48.760 43.720 54.42 10884 12 48.840 43.740 54.44 10888 13 48.860 43.820 54.52 10904 14 48.920 43.840 54.54 10908 15 49.020 43.920 54.62 10924 16 49.080 43.960 54.66 10932 17 49.100 44.120 54.82 10964 18 49.160 44.160 54.86 10972 19 49.200 44.180 54.88 10976 20 49.240 44.200 54.90 10980 21 49.260 44.320 55.02 11004 22 49.360 44.360 55.06 11012 23 49.400 44.400 55.10 11020 24 49.460 44.460 55.16 11032 25 49.500 44.480 55.18 11036
30 u3600bm 4516c?ct0?08/02 usa modulation loop frequencies and dividers n channel p m q m f mod (mhz) 1 13 157 7.640 213957.485 3 13 105 7.510 4 13 157 7.640 5 13 123 7.555 6 13 157 7.640 7 13 157 7.640 8 13 157 7.640 9 13 157 7.640 10 13 181 7.700 new channel n channel p m q m f mod (mhz) 11 10 34 5.66 12 10 10 5.60 13 10 34 5.66 14 10 18 5.62 15 10 10 5.60 16 10 2 5.58 17 10 58 5.72 18 10 50 5.70 19 10 42 5.68 20 10 34 5.66 21 10 66 5.74 22 10 50 5.70 23 10 50 5.70 24 10 50 5.70 25 10 42 5.68
31 u3600bm 4516c?ct0?08/02 portugal modulation loop frequency and divider f ref1 = 557.5 khz/4, f mod = 1.25 mhz/4,p m = 8,q m = 216, m = 4 portugal base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 01 10 00 1 11 001 10 1 11 1 1 value d1 = 2d2 = 8d3 = 4 infra m = 4 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 27.550 37.000 26.300 4208 2 27.575 37.025 26.325 4212 3 27.600 37.050 26.350 4216 4 27.625 37.075 26.375 4220 5 27.650 37.100 26.400 4224 6 27.675 37.125 26.425 4228 7 27.700 37.150 26.450 4232 8 27.725 37.175 26.475 4236 9 27.750 37.200 26.500 4240 10 27.775 37.225 26.525 4244 11 27.800 37.250 26.550 4248 12 27.825 37.275 26.575 4252
32 u3600bm 4516c?ct0?08/02 portugal modulation loop frequency and divider f ref1 = 557.5 khz/4, f mod = 1.25 mhz/4,p m = 8,q m = 216, m = 4 portugal hand country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 01 01 00 1 11 001 10 0 11 1 1 value d1 = 2d2 = 8d3 = 4 supra m = 4 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 37.000 27.550 38.250 6120 2 37.025 27.575 38.275 6124 3 37.050 27.600 38.300 6128 4 37.075 27.625 38.325 6132 5 37.100 27.650 38.350 6136 6 37.125 27.675 38.375 6140 7 37.150 27.700 38.400 6144 8 37.175 27.725 38.425 6148 9 37.200 27.750 38.450 6152 10 37.225 27.775 38.475 6156 11 37.250 27.800 38.500 6160 12 37.275 27.825 38.525 6164
33 u3600bm 4516c?ct0?08/02 taiwan modulation loop frequency and divider f mod = 7.7 mhz, p m = 13,q m = 181, m = 1 taiwan base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 00 01 1 00 110 01 1 00 1 1 value max d1 = 8 d2 = 8 d3 = 1 infra m = 1 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 45.2500 48.2500 37.5500 6008 2 45.2750 48.2750 37.5750 6012 3 45.3000 48.3000 37.6000 6016 4 45.3250 48.3250 37.6250 6020 5 45.3500 48.3500 37.6500 6024 6 45.3750 48.3750 37.6750 6028 7 45.4000 48.4000 37.7000 6032 8 45.4250 48.4250 37.7250 6036 9 45.4500 48.4500 37.7500 6040 10 45.4750 48.4750 37.7750 6044
34 u3600bm 4516c?ct0?08/02 taiwan modulation loop frequency and divider f mod = 7.7 mhz, p m = 13,q m = 181, m = 1 taiwan hand country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 00 01 1 00 110 00 0 00 1 1 value max d1 = 8 d2 = 8 d3 = 1 supra m = 1 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 48.2500 45.2500 55.9500 8952 2 48.2750 45.2750 55.9750 8956 3 48.3000 45.3000 56.0000 8960 4 48.3250 45.3250 56.0250 8964 5 48.3500 45.3500 56.0500 8968 6 48.3750 45.3750 56.0750 8972 7 48.4000 45.4000 56.1000 8976 8 48.4250 45.4250 56.1250 8980 9 48.4500 45.4500 56.1500 8984 10 48.4750 45.4750 56.1750 8988
35 u3600bm 4516c?ct0?08/02 china modulation loop frequency and divider f mod = 7.7 mhz, p m = 13,q m = 181, m = 1 china base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 00 01 1 00 110 01 1 00 1 1 value max d1 = 8 d2 = 8 d3 = 1 infra m = 1 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 45.0000 48.0000 37.3000 5968 2 45.0250 48.0250 37.3250 5972 3 45.0500 48.0500 37.3500 5976 4 45.0750 48.0750 37.3750 5980 5 45.1000 48.1000 37.4000 5984 6 45.1250 48.1250 37.4250 5988 7 45.1500 48.1500 37.4500 5992 8 45.1750 48.1750 37.4750 5996 9 45.2000 48.2000 37.5000 6000 10 45.2250 48.2250 37.5250 6004 11 45.2500 48.2500 37.5500 6008 12 45.2750 48.2750 37.5750 6012 13 45.3000 48.3000 37.6000 6016 14 45.3250 48.3250 37.6250 6020 15 45.3500 48.3500 37.6500 6024 16 45.3750 48.3750 37.6750 6028 17 45.4000 48.4000 37.7000 6032 18 45.4250 48.4250 37.7250 6036 19 45.4500 48.4500 37.7500 6040 20 45.4750 48.4750 37.7750 6044
36 u3600bm 4516c?ct0?08/02 china modulation loop frequency and divider f mod = 7.7 mhz, p m = 13,q m = 181, m = 1 china hand country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 00 01 1 00 110 00 0 00 1 1 value max d1 = 8 d2 = 8 d3 = 1 supra m = 1 high low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 48.000 45.0000 55.7000 8912 2 48.0250 45.0250 55.7250 8916 3 48.0500 450500 55.7500 8920 4 48.0750 450750 55.7750 8924 5 48.1000 45.1000 55.8000 8928 6 48.1250 45.1250 55.8250 8932 7 48.1500 45.1500 55.8500 8936 8 48.1750 45.1750 55.8750 8940 9 48.2000 45.2000 55.9000 8944 10 48.2250 45.2250 55.9250 8948 11 48.2500 45.2500 55.9500 8952 12 48.2750 45.2750 55.9750 8956 13 48.3000 45.3000 56.0000 8960 14 48.3250 45.3250 56.0250 8964 15 48.3500 45.3500 56.0500 8968 16 48.3750 45.3750 56.0750 8972 17 48.4000 45.4000 56.1000 8976 18 48.4250 45.4250 56.1250 8980 19 48.4500 45.4500 56.1500 8984 20 48.4750 45.4750 56.1750 8988
37 u3600bm 4516c?ct0?08/02 new zealand modulation loop frequency and divider f mod = 4.7 mhz/4, p m = 8,q m = 96, m = 1 new zealand base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 00 01 11 1 01 110 01 1 00 0 1 value d1 = 4d2 = 8d3 = 2 infra m = 1 low low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 11 34.2500 40.2500 29.5500 4728 12 34.2750 40.2750 29.5750 4732 13 34.3000 40.3000 29.6000 4736 14 34.3250 40.3250 29.6250 4740 15 34.3500 40.3500 29.6500 4744 16 34.3750 40.3750 29.6750 4748 17 34.4000 40.4000 29.7000 4752 18 34.4250 40.4250 29.7250 4756 19 34.4500 40.4500 29.7500 4760 20 34.4750 40.4750 29.7750 4764
38 u3600bm 4516c?ct0?08/02 new zealand modulation loop frequency and divider f mod = 4.7 mhz/4, p m = 8,q m = 96, m = 1 new zealand hand country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 00 01 11 1 01 101 01 0 00 0 1 value max min d1 = 4d2 = 8d3 = 2 supra m = 1 low low gain channel frequencies and 1st lo divider, f ref3 = 6.25 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 11 40.2500 34.2500 44.9500 7192 12 40.2750 34.2750 44.9750 7196 13 40.3000 34.3000 45.0000 7200 14 40.3250 34.3250 45.0250 7204 15 40.3500 34.3500 45.0500 7208 16 40.3750 34.3750 45.0750 7212 17 40.4000 34.4000 45.1000 7216 18 40.4250 34.4250 45.1250 7220 19 40.4500 34.4500 45.1500 7224 20 40.4750 34.4750 45.1750 7228
39 u3600bm 4516c?ct0?08/02 korea base country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 00 01 1 00 100 00 1 00 1 1 value max d1 = 8 d2 = 8 d3 = 1 infra m = 1 high high gain channel frequencies and 1st lo divider, f ref3 = 5 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 46.6100 49.6700 38.9700 7794 2 46.6300 49.8450 39.1450 7829 3 46.6700 49.8600 39.1600 7832 4 46.7100 49.7700 39.0700 7814 5 46.7300 49.8750 39.1750 7835 6 46.7700 49.8300 39.1300 7826 7 46.8300 49.8900 39.1900 7838 8 46.8700 49.9300 39.2300 7846 9 46.9300 49.9900 39.2900 7858 10 46.9700 49.9700 39.2700 7854 11 46.5100 49.6950 39.9950 7799 12 46.5300 49.7100 39.0100 7802 13 46.5500 49.7250 39.0250 7805 14 46.5700 49.7400 39.0400 7808 15 46.5900 49.7550 39.0550 7811
40 u3600bm 4516c?ct0?08/02 korea hand country setting name ra1[1:0] ra2[1:0] d1[1:0] d20 d3[1:0] kv2[3:1] gmod[1:0] imixi dr1i[1:0] frmt gdem setting 10 00 01 1 00 100 00 0 00 1 1 value max d1 = 8 d2 = 8 d3 = 1 supra m = 1 high high gain channel frequencies and 1st lo divider, f ref3 = 5 khz channel number tx channel frequency (mhz) rx channel frequency (mhz) f lo = 1/2 f vco3 (mhz) dv3i[14:0] = n 1 49.6700 46.6100 57.3100 11462 2 49.8450 46.6300 57.3300 11466 3 49.8600 46.6700 57.3700 11474 4 49.7700 46.7100 57.4100 11482 5 49.8750 46.7300 57.4300 11486 6 49.8300 46.7700 57.4700 11494 7 49.8900 46.8300 57.5300 11506 8 49.9300 46.8700 57.5700 11514 9 49.9900 46.9300 57.6300 11526 10 49.9700 46.9700 57.6700 11534 11 49.6950 46.5100 57.2100 11442 12 49.7100 46.5300 57.2300 11446 13 49.7250 46.5500 57.2500 11450 14 49.7400 46.5700 57.2700 11454 15 49.7550 46.5900 57.2900 11458
41 u3600bm 4516c?ct0?08/02 korea modulation loop frequencies and dividers crystal specifications drive level < 0.01 w note: (1) necessary to stay within adjustment range of oscillator faos (0:2) = 0 ... 5 n channel p m q m f mod (mhz) 1 13 157 7.640 213957.485 3 13 105 7.510 4 13 157 7.640 5 13 123 7.555 6 13 157 7.640 7 13 157 7.640 8 13 157 7.640 9 13 157 7.640 10 13 181 7.700 11 13 107 7.515 12 13 109 7.520 13 13 111 7.525 14 13 113 7.530 15 13 115 7.535 parameters symbol min. typ. max. unit load resonance frequency with 14 pf load capacitance 11.15 mhz load capacitance 14 pf frequency tolerance ?30 +30 ppm shunt capacitance 3.1 pf motional capacitance 9.2 ff (1) series resistance 20
42 u3600bm 4516c?ct0?08/02 package information ordering information extended type number package remarks U3600BM-NFN sso44 tube U3600BM-NFNg3 sso44 taped and reeled technical drawings according to din specifications package sso44 dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22
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